1. Field of Invention
The invention relates to a thin-film transistor (TFT) fabrication method and, in particular, to a fabrication method of TFT using four-mask process.
2. Related Art
FIGS. 1A to 1F show the cross-sectional views of a conventional TFT fabrication method. As shown in FIG. 1A, a first metal is deposited on an insulating substrate 100 by sputtering (not shown). The first metal layer is etched to form a gate 101 on the substrate 100. The substrate 100 is alkaline-free glass. The first metal layer can be an Al, Cr or Mo layer. The etching process is a wet etching process.
As shown in FIG. 1B, the plasma enhanced chemical vapor deposition (PECVD) method is employed to deposit a gate insulation layer 102, a semiconductor layer 103, and an ohmic contact layer 104 on the substrate 100 to cover the gate 101 in sequence. A Photolithographic and etching process is used to pattern the semiconductor layer 103 and the ohmic contact layer 104, and then a patterned ohmic contact layer 104 and a patterned semiconductor layer 103 are formed. The etching method is a dry etching process. The semiconductor layer 103 is an amorphous silicon layer. The ohmic contact layer 104 is an n-doped amorphous silicon layer. The gate insulation layer 102 is a silicon nitride layer.
As shown in FIGS. 1C and 1D, a second metal layer 105 is deposited on the ohmic contact layer 104 by sputtering to cover the gate insulation layer 102. A photolithographic and etching process is employed to etch the second metal layer 105, and then the second metal layer 105 is patterned to form a source 105a and a drain 105b. A back channel etching (BCE) process is used to etch the ohmic contact layer 104 and the semiconductor layer 103 to form a channel region 106. The second metal layer 105 may be an Al, Cr, or Mo layer.
As shown in FIG. 1E, the PECVD method is used to deposit a passivation layer 107 over the substrate 100, covering the patterned second metal layer 105 and the gate insulation layer 102. A photolithographic and etching process is employed to etch the passivation layer 107 to form a patterned passivation layer 107. A contact hole 108 is formed above the drain 105b. The passivation layer 107 is a silicon nitride layer.
As shown in FIG. 1F, a pixel electrode layer 109 is deposited on the substrate 100 by sputtering. A photolithographic and etching process is employed to pattern the pixel electrode layer 109. The pixel electrode layer 109 is made of indium tin oxide (ITO).